Dr Vincent O'Brien

PhD MEng BSc

Assistant Lecturer

Faculty of Engineering, Carlow Campus
e: vincent.obrien@itcarlow | t: 059 9175463
ORCID ID:0000-0002-8209-6661      LinkedIn

Dr Vincent O’Brien has a BSc in Electronic Systems and an MEng and PhD degree in Electronic Engineering from the University of Limerick. He was previously a research assistant and postdoctoral researcher at the Circuits and Systems Research Centre in the University of Limerick. He is currently an assistant lecturer within the Aeronautical, Mechanical and Electronic Engineering department at  SETU Carlow.

  • Research Interests
  • Publications
  • Research Supervision
  • Engagement and Collaboration

Research Interests

Dr O’Brien’s research activities involve the development of embedded systems incorporating built-in-self-test algorithms and hardware to enable on-chip testing of embedded data converters. His PhD research focused on the design of digital signal processing algorithms to correct errors in oversampling data converters. Currently, his research focuses on the development of embedded systems used to deploy artificial intelligence at the network edge.


Peer Reviewed Journal Articles

S. Mehta, D. O’Hare, V. O’Brien, E. Thompson, and B. Mullane (2020) "Analysis and Design of a Tri-Level Current-Steering DAC with 12-bit Linearity and Improved Impedance Matching Suitable for CT-ADCs," IEEE Open Journal of Circuits and Systems, pp. 34-47, 2020.

O’Brien V. and Mullane B. (2019) "High Order Mismatch Shaping for Low Oversampling Rates," in IEEE Transactions on Circuits and Systems II: Express Briefs.

O'Brien V., Scanlan A., and Mullane B. (2017) 'A Reduced Hardware ISI and Mismatch Shaping DEM Decoder'. Springer Circuits Systems and Signal Processing Journal.

Scanlan, A., O'Hare D., Halton M., O'Brien V., Mullane Brendan and Thompson, Eric (2017) 'Analysis of feedback predictive encoder based ADCs'. Compel-The International Journal For Computation And Mathematics In Electrical And Electronic Engineering, 36 (1):129-152.

Books and Book Chapters

Mullane B. and O'Brien V. (2012), "A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a Low Voltage CMOS Process," in VLSI-SoC Book: Technologies for Systems Integration, S. Mir, C. S. Choy, C. Tsui, and R. Reis, Eds., ed: Springer, 2012.

Conference Presentations

S. Mehta, V. O’Brien, B. Mullane, R. Pelliconi, C. Erdmann, and B. Farley (2020) "A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC,"27th IEEE ICECS conference, 23-25 November 2020

Mullane B. and O’Brien V. (2018) "An in-Place Processor Design for Real-Value FFTs Targeting in-Situ Dynamic ADC Test," 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, Canada, 2018.

Mooney J., O’Brien V., Halton M. and Iordanov P. (2015). “Dithered Multi-Bit Sigma-Delta Modulator Based DPWM for DC-DC Converters”, Accepted to IEEE Applied Power Electronics Conference APEC ’15, Charlotte, North Carolina, 2015.

O’Brien V. and Mullane B. (2014), “High Order Dynamic Element Matching for Multi-bit Delta Sigma A/D & D/A Converters”, IET Irish Signals and Systems Conference ISSC '14, UL, Ireland, June 2014.

Mo H., Kennedy M. P., O'Brien V. and Mullane B. (2013), "Experimental Validation of DAC with Nested Bus-Splitting EFM4 DDSM," Circuit Theory and Design (ECCTD), 21st IEEE European Conference on, Dresden, 2013.

Mullane, B. and O'Brien V. (2011), “A high performance band-pass DAC architecture and design targeting a low voltage silicon process”, Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Hong Kong, 2011.

O'Brien, V. and Mullane B. (2011), “High Order Mismatch Noise Shaping for Bandpass DACs”, 18th IEEE International Conference in Electronics, Circuits, and Systems (ICECS), 2011.

O'Brien V., Mullane M., Fleischmann T., and MacNamee C. (2009). "A High Precision Analog Signal Generator Design for ADC BIST," in European Test Symposium, 2009. ETS '09. 14th IEEE, pp. 125-130, 2009.

Mullane B., O'Brien V., MacNamee C., and Fleischmann T. (2009). "A prototype platform for system-on-chip ADC test and measurement," in SOC Conference, SOCC 2009. IEEE International, pp. 169-172, 2009.

Mullane B., O'Brien V., MacNamee C., and Fleischmann T. (2009). "A2DTest: A complete integrated solution for on-chip ADC self-test and analysis," in Test Conference. ITC 2009. International, pp. 1-10, 2009.

Mullane B., O'Brien V., MacNamee C., and Fleischmann T. (2009). "An SOC Platform for ADC Test and Measurement," in Design and Diagnostics of Electronic Circuits and Systems, DDECS '09, IEEE, pp. 1-4, 2009.

Mullane B., MacNamee C., O'Brien V., and Flesichmann T.(2009). "An On-Chip Solution for Static ADC Test and Measurement," in Proceedings of the 19th ACM Great Lakes symposium on VLSI Boston, MA, USA: ACM, 2009.

Mullane B., MacNamee C., O'Brien V., and Fleischmann T. (2009). "A Low Cost On-Chip Design Platform for Static ADC Measurements," in European Test Symposium, ETS '09, 14th IEEE, pp. 125-130, 2009.


O'Brien V., Mullane B. (2015) Patent US 9762258 B2, “Mismatch and Inter Symbol Interference (ISI) shaping using Dynamic Element Matching”.

Mullane B., O'Brien V., Fleischmann T. (2009). Patent Application: PA Ref. UNI0052, On-Chip Testing – A programmable on-chip test and measurement platform for Analog to Digital Converters.


Research Supervision

Co-supervisor on an MSc project in the area of Machine Learning. The research conducted by Ryan Furlong (ITCarlow) is a study of Sub-discrimination within Metric Embeddings.

Co-supervised PhD project conducted by Shantanu Metha (University of Limerick).  Shantanu’s thesis is titled “Nyquist-Rate Current-Steering D/A Converter Error Analysis, Modelling and Mitigation Techniques”.

Areas of Interest for Future Supervisory role
  • Embedded Systems
  • Data Converters
  • Applied Signal Processing
  • Machine Learning


Engagement and Collaboration

BISTPAD - “Built In Self-Test Processing engine for data converters”, Enterprise Ireland Commercialisation Fund (2017)

  • Development of a processing engine capable of capturing and analyzing on-chip data converter signals. Provide a method to evaluate and test data converters in situ.

DEMopt - “Dynamic Element Matching for Oversampled Data Converters”, Enterprise Ireland Innovation Partnership Award. (2014)

  • Research and design of dynamic element matching scheme for shaping mismatch and intersymbol interference errors in oversampling A/D and D/A converters. Project in conjunction with Analog Devices Ireland

CTU4ADC - “A Calibration and Self-test Unit for Analog to Digital Converters”, Microelectronics Circuits Centre Ireland Award. (2011)

  • Research methods to test and calibrate ADCs in an embedded environment, algorithms implemented on Xilinx FPGA hardware

SEDACA - “A Scaleable Efficient Digital to Analog Converter Architecture”, Microelectronics Circuits Centre Ireland (MCCI) Award. (2009)

  • Design, build and test a Sigma Delta band-pass D/A converter incorporating high order mismatch shaping on UMC 90nm process

ProgDFT - “The Generation of a Novel Programmable Design for Test and Debug Platform” Enterprise Ireland Commercial Technology Development (2007)

  • Research and design of a programmable on-chip ADC test platform. Test chip prototyped on Xilinx FPGA platform